The present invention generally relates to digital audio reproducing apparatuses, and more particularly to a digital audio reproducing apparatus such as a compact disk (CD) player, a digital audio tape recorder (DAT) and the like.
FIG. 1 shows an example of a conventional CD player. In FIG. 1, a recording medium reading part 10 reads a high-frequency signal which is recorded on a recording medium (CD) 11, and supplies this high-frequency signal to a radio frequency (RF) amplifier 12 wherein the signal is amplified. The amplified high-frequency signal is supplied to a phase detector 16 of a phase locked loop (PLL) circuit 15 via a reproduced signal processing part 14. The PLL circuit 15 includes the phase detector 16, a voltage controller oscillator (VCO) 17 and a frequency dividing circuit 18. The PLL circuit 15 generates a reproducing clock based on the high-frequency signal, and supplies the reproducing clock to the reproduced signal processing part 14.
For example, an integrated circuit (IC) chip CXA1801 may be used for the RF amplifier 12, and an IC chip CXD2500 may be used for the reproduced signal processing part 14, the phase detector 16 and the frequency dividing circuit 18.
The reproduced signal processing part 14 extracts bits of the high-frequency signal using the reproducing clock, demodulates the reproduced signal in frame synchronism, and carries out processes such as interleaving and error correction so as to reproduce digital audio data. The digital audio data is converted into an analog signal in a digital-to-analog (D/A) converter 19, and the analog signal is supplied to an audio circuit (not shown) in the next stage via a terminal 20. In addition, a servo signal processing part 21 carries out a focus servo operation and a tracking servo operation based on the high-frequency signal, and also carries out a spindle servo operation so that the bit clock synchronization is maintained constant.
For example, an IC chip CXA1372 may be used for the servo signal processing part 21.
A system control microprocessor 22 controls the entire operation of the CD player. More particularly, the system control microprocessor 22 instructs the operations of the reproduced signal processing part 14 and the servo signal processing part 21. When an external instruction is supplied to the system control microprocessor 22 via a terminal 23 so as to change the reproducing speed, the system control microprocessor 22 controls the frequency dividing ratio of the frequency dividing circuit 18 within the PLL circuit 15 so as to vary the frequency of the reproducing clock which is output from the VCO 17. As a result, the data transmission rate of the entire CD player changes, and the transmission rate of the digital audio data which is supplied to the D/A converter 19 also changes.
For this reason, if the reproducing speed is varied, the transmission rate of the entire CD player changes and the sampling frequency of the D/A converter 19 also changes. Consequently, there is a problem in that the key (musical interval or step) becomes higher if the reproducing speed of the audio increases. On the other hand, there is a problem in that the key becomes lower if the reproducing speed of the audio decreases.
For example, a Japanese Laid-Open Patent Application No. 62-231999 proposes an apparatus in which a reproducing speed of a reproducing unit and a key conversion of a key conversion unit are controlled simultaneously. In addition, a Japanese Laid-Open Patent Application No. 63-138399 proposes an apparatus in which a relationship between a first rate of change of the key obtained by controlling the reproducing speed of the reproducing unit and a second rate of change of the key obtained by controlling the key conversion unit is set to a value which is determined by a desired reproducing speed and key.
However, although the Japanese Laid-Open Patent Applications No. 62-231999 and No. 63-138399 generally describe the control methods, no specific construction is disclosed therein for realizing the proposed control methods. In other words, no specific circuit constructions are disclosed, and the disclosures seem insufficient for the purposes of realizing the proposed apparatuses.